Semiconductor devices, such as complementary metal-oxide semiconductor (CMOS) transistors, are widely used in applications requiring high-speed, low power digital circuits including microprocessors, memory devices and gate arrays. These semiconductor devices are typically fabricated by bonding silicon dioxide layers on a silicon substrate. The silicon dioxide layers are selectively etched away with a plasma current to expose the silicon substrate. Exposed silicon on either side of a non-etched area is implanted with ions to create source and drain areas. A conductive layer is deposited on the non-exposed area to create a gate for the transistor. Additional conductive layers are disposed on the source and drain areas to provide electrical connection thereto. The conductive layers are typically separated by a dielectric material. Multiple layers of conductive material are also disposed elsewhere on the substrate to provide pads for external connection to the transistor. The pads are typically connected to the transistor by the conductive layers and the interlayer connections therebetween.
During the numerous steps required to manufacture semiconductor devices, the silicon substrate needs to be isolated from interconnects which will be located above it. Several steps are typically taken to accomplish such isolation. The first isolation step typically consists of disposing a nitride stop layer above the silicon substrate and field oxide. Thereafter, an oxide layer is typically disposed above the nitride stop layer.
A common problem which can occur at the interface of the nitride stop layer and the oxide layer is to have small bubble-like defects which in turn cause exaggerated defects on the surface of the oxide layer. These defects typically cause reliability problems and can cause poison contact problems.
It is possible to eliminate these defects by using a wet cleaning step such as RCA and HF dip. However, utilizing a wet cleaning step can cause pinholes on the very thin nitride layer. Additionally, this solution requires an extra step, resulting in longer cycle times, and additional wafer handling which can add additional particles and scratches.
What is needed is a device in which these defects are eliminated, and a method for eliminating these defects which improves reliability, reduces cost of manufacturing, and simplifies manufacturing. The present invention addresses such a need.